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final publication# 17713 rev: e amendment/ 0 issue date: november 1998 com?:-10 ind:-20 pallv16v8-10 and pallv16v8z-20 low voltage, zero power 20-pin ee cmos universal programmable array logic distinctive characteristics low-voltage operation, 3.3 v jedec compatible ? cc = +3.0 v to +3.6 v pin and function compatible with all 20-pin pal devices electrically-erasable cmos technology provides recon?urable logic and full testability direct plug-in replacement for the pal16r8 series designed to interface with both 3.3-v and 5-v logic outputs programmable as registered or combinatorial in any combination programmable output polarity programmable enable/disable control preloadable output registers for testability automatic register reset on power up cost-effective 20-pin plastic dip, plcc, and soic packages extensive third-party software and programmer support fully tested for 100% programming and functional yields and high reliability general description the pallv16v8 is an advanced pal device built with low-voltage, high-speed, electrically-erasable cmos technology. it is functionally compatible with all 20-pin gal devices. the macrocells provide a universal device architecture. the pallv16v8 will directly replace the pal16r8, with the exception of the pal16c1. the pallv16v8z provides zero standby power and high speed. at 30- a maximum standby current, the pallv16v8z allows battery powered operation for an extended period. the pallv16v8 utilizes the familiar sum-of-products (and/or) architecture that allows users to implement complex logic functions easily and ef?iently. multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in pal devices. the equations are programmed into the device through ?ating-gate cells in the and logic array that can be erased electrically. the ?ed or array allows up to eight data product terms per output for logic functions. the sum of these products feeds the output macrocell. each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. the output con?uration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.
2 pallv16v8-10 and pallv16v8z-20 families block diagram functional description the pallv16v8 is a low-voltage, ee cmos version of the palce16v8. the pallv16v8z is a low-voltage, ee cmos version of the palce16v8. in addition, the pallv16v8z has zero standby power and an unused product term disable feature for reduced power consumption. the pallv16v8 is a universal pal device. it has eight independently con?urable macrocells (mc 0 -mc 7 ). each macrocell can be con?ured as registered output, combinatorial output, combinatorial i/o or dedicated input. the programming matrix implements a programmable and logic array, which drives a ?ed or logic array. buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. pins 1 and 11 serve either as array inputs or as clock (clk) and output enable (oe ), respectively, for all ?p-?ps. unused input pins should be tied directly to v cc or gnd. product terms with all bits unprogrammed (disconnected) assume the logical high state and product terms with both true and complement of any input signal connected assume a logical low state. the programmable functions on the pallv16v8 are automatically con?ured from the user? design speci?ation. the design speci?ation is processed by development software to verify the design and create a programming ?e. this ?e, once downloaded to a programmer, con?ures the device according to the user? desired function. programmable and array 32 x 64 macro mc 0 macro mc 1 macro mc 2 macro mc 3 macro mc 4 macro mc 5 macro mc 6 macro mc 7 oe /i 9 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 8 i 1 - i 8 clk/ i0 17713d-1 i/o 5 i/o 6 i/o 7
pallv16v8-10 and pallv16v8z-20 families 3 the user is given two design options with the pallv16v8. first, it can be programmed as a standard pal device from the pal16r8 and pal10h8 series. the pal programmer manufacturer will supply device codes for the standard pal device architectures to be used with the pallv16v8. the programmer will program the pallv16v8 in the corresponding architecture. this allows the user to use existing standard pal device jedec ?es without making any changes to them. alternatively, the device can be programmed as a pallv16v8. here the user must use the pallv16v8 device code. this option allows full utilization of the macrocell. configuration options each macrocell can be con?ured as one of the following: registered output, combinatorial output, combinatorial i/o, or dedicated input. in the registered output con?uration, the output buffer is enabled by the oe pin. in the combinatorial con?uration, the buffer is either controlled by a product term or always enabled. in the dedicated input con?uration, it is always disabled. with the exception of mc 0 and mc 7 , a macrocell con?ured as a dedicated input derives the input signal from an adjacent i/o. mc 0 derives its input from pin 11 (oe ) and mc 7 from pin 1 (clk). the macrocell con?urations are controlled by the con?uration control word. it contains 2 global bits (sg0 and sg1) and 16 local bits (sl0 0 through sl0 7 and sl1 0 through sl1 7 ). sg0 determines whether registers will be allowed. sg1 determines whether the pallv16v8 will emulate a pal16r8 family. within each macrocell, sl0 x , in conjunction with sg1, selects the con?uration of the macrocell, and sl1 x sets the output as either active low or active high for the individual macrocell. the con?uration bits work by acting as control inputs for the multiplexers in the macrocell. there are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. sg1 and sl0 x are the control signals for all four multiplexers. in mc 0 and mc 7 , 1 0 0 1 17713d-004 *in macrocells mc 0 and mc 7 , sg1 is replaced by sg0 on the feedback multiplexer. 1 1 0 x *sg1 sg1 sl0 x dq q 1 0 1 1 0 x 1 1 1 0 0 0 v cc clk sl0 x oe to adjacent macrocell from adjacent pin 1 1 0 x 1 0 sl1 x i/o x figure 1. pallv16v8 macrocell
4 pallv16v8-10 and pallv16v8z-20 families sg0 replaces sg1 on the feedback multiplexer. this accommodates clk being the adjacent pin for mc 7 and oe the adjacent pin for mc 0 . registered output con?uration the control bit settings are sg0 = 0, sg1 = 1 and sl0 x =0. there is only one registered con?uration. all eight product terms are available as inputs to the or gate. data polarity is determined by sl1 x . the ?p-?p is loaded on the low-to-high transition of clk. the feedback path is from q on the register. the output buffer is enabled by oe . combinatorial con?urations the pallv16v8 has three combinatorial output con?urations: dedicated output in a non- registered device, i/o in a non-registered device and i/o in a registered device. dedicated output in a non-registered device the control bit settings are sg0 = 1, sg1 = 0 and sl0 x =0. all eight product terms are available to the or gate. although the macrocell is a dedicated output, the feedback is used, with the exception of mc 3 and mc 4 . mc 3 and mc 4 do not use feedback in this mode. because clk and oe are not used in a non-registered device, pins 1 and 11 are available as input signals. pin 1 will use the feedback path of mc 7 , and pin 11 will use the feedback path of mc 0 . combinatorial i/o in a non-registered device the control bit settings are sg0 = 1, sg1 = 1, and sl0 x =1. only seven product terms are available to the or gate. the eighth product term is used to enable the output buffer. the signal at the i/o pin is fed back to the and array via the feedback multiplexer. this allows the pin to be used as an input. because clk and oe are not used in a non-registered device, pins 1 and 11 are available as inputs. pin 1 will use the feedback path of mc 7 , and pin 11 will use the feedback path of mc 0 . combinatorial i/o in a registered device the control bit settings are sg0 = 0, sg1 = 1 and sl0 x =1. only seven product terms are available to the or gate. the eighth product term is used as the output enable. the feedback signal is the corresponding i/o signal. dedicated input con?uration the control bit settings are sg0 = 1, sg1 = 0 and sl0 x =1. the output buffer is disabled. except for mc 0 and mc 7 , the feedback signal is an adjacent i/o. for mc 0 and mc 7 , the feedback signals are pins 1 and 11. these con?urations are summarized in table 1 and illustrated in figure 2.
pallv16v8-10 and pallv16v8z-20 families 5 programmable output polarity the polarity of each macrocell can be active-high or active-low, either to match output signal needs or to reduce product terms. programmable polarity allows boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. it can also save ?emorganizing?efforts. selection is through a programmable bit sl1 x which controls an exclusive-or gate at the output of the and/or logic. the output is active high if sl1 x is 1 and active low if sl1 x is 0. table 1. macrocell con?uration sg0 sg1 sl0 x cell con?uration devices emulated sg0 sg1 sl0 x cell con?uration devices emulated device uses registers device uses no registers 010 registered output pal16r8, 16r6, 16r4 100 combinatorial output pal10h8, 12h6, 14h4, 16h2, 10l8, 12l6, 14l4, 16l2 011 combinatorial i/o pal16r6, 16r4 1 0 1 input pal12h6, 14h4, 16h2, 12l6, 14l4, 16l2 111 combinatorial i/o pal16l8
6 pallv16v8-10 and pallv16v8z-20 families figure 2. macrocell con?urations 17713d-5 d q oe clk a. registered active low dq oe clk b. registered active high c. combinatorial i/o active low d. combinatorial i/o active high e. combinatorial output active low v cc f. combinatorial output active high v cc adjacent i/o pin g. dedicated input n otes: . feedback is not available on pins 15 and 16 in the combinatorial output mode. . the dedicated-input con?uration is not available on pins 15 and 16. note 1 note 1 note 2 q q
pallv16v8-10 and pallv16v8z-20 families 7 bene?s of lower operating voltage the pallv16v8 has an operating voltage range of 3.0v to 3.6 v. low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for notebook applications. the pallv16v8 inputs accept up to 5.5 v, so they are safe for mixed voltage design. because power is proportional to the square of the voltage, reduction of the supply voltage from 5.0 v to 3.3 v signi?antly reduces power consumption. this directly translates to longer battery life for portable applications. lower power consumption can also be used to reduce the size and weight of the battery. thus, 3.3-v designs facilitate a reduction in the form factor. a lower operating voltage results in a reduction of i/o voltage swings. this reduces noise generation and provides a less hostile environment for board design. a lower operating voltage also reduces electromagnetic radiation noise and makes obtaining fcc approval easier. power-up reset all ?p-?ps power up to a logic low for predictable system initialization. outputs of the pallv16v8 will depend on whether they are selected as registered or combinatorial. if registered is selected, the output will be high. if combinatorial is selected, the output will be a function of the logic. register preload the register on the pallv16v8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. this feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. in addition, transitions from illegal states can be veri?d by loading illegal states and observing proper recovery. the preload function is not disabled by the security bit. this allows functional testing after the security bit is programmed. security bit a security bit is provided on the pallv16v8 as a deterrent to unauthorized copying of the array con?uration patterns. once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. however, programming and veri?ation are also defeated by the security bit. the bit can only be erased in conjunction with the array during an erase cycle. electronic signature word an electronic signature word is provided in the pallv16v8 device. it consists of 64 bits of programmable memory that can contain user-de?ed data. the signature data is always available to the user independent of the security bit. programming and erasing the pallv16v8 can be programmed on standard logic programmers. it also may be erased to reset a previously con?ured device back to its unprogrammed state. erasure is automatically performed by the programming hardware. no special erase operation is required.
8 pallv16v8-10 and pallv16v8z-20 families quality and testability the pallv16v8 offers a very high level of built-in quality. the erasability if the device provides a direct means of verifying performance of all the ac and dc parameters. in addition, this veri?s complete programmability and functionality of the device to yield the highest programming yields and post-programming function yields in the industry. technology the high-speed pallv16v8z is fabricated with vantis?advanced electrically-erasable (ee) cmos process. the array connections are formed with proven ee cells. this technology provides strong input-clamp diodes and a grounded substrate for clean switching. zero-standby power mode the pallv16v8 features a zero-standby power mode. when none of the inputs switch for an extended period (typically 50 ns), the pallv16v8z will go into standby mode, shutting down most of its internal circuitry. the current will go to almost zero (i cc < 30 a). the outputs will maintain the states held before the device went into the standby mode. there is no speed penalty associated with coming out of standby mode. when any input switches, the internal circuitry is fully enabled, and power consumption returns to normal. this feature results in considerable power savings for operation at low to medium frequencies. this saving is illustrated in the i cc vs. frequency graph. the pallv16v8z-20 has the free-running-clock feature. this means that if one or more registers are used, switching only the clk will not wake up the logic array or any macrocell. the device will not be in standby mode because the clk buffer will draw some current, but dynamic i cc will typically be less than 2 ma. product-term disable on a programmed pallv16v8z, any product terms that are not used are disabled. power is cut off from these product terms so that they do not draw current. as shown in the i cc vs. frequency graph, product-term disabling results in considerable power savings. this saving is greater at the higher frequencies. further hints on minimizing power consumption can be found in a separate document entitled, minimizing power consumption with zero-power plds .
pallv16v8-10 and pallv16v8z-20 families 9 logic diagram 034781112151619202324272831 0 7 8 15 16 23 24 31 03478111215161920 24272831 23 i 2 i 1 clk/i 0 1 2 3 i 4 i 3 4 5 clk oe 1 1 0 x 1 0 sg1 sl0 7 1 1 0 x 1 0 sg1 sl0 5 1 1 0 x 1 0 sg1 sl0 4 sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 5 0 x sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 4 0 x 1 1 0 x 1 0 sg1 sl0 6 sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 6 0 x sg0 1 1 0 x 1 0 dq q 1 0 1 1 0 x 1 1 1 0 0 0 0 1 v cc 17 i/o 4 16 18 i/o 5 i/o 6 i/o 7 19 sl1 7 sl1 6 sl1 5 sl1 4 20 v cc sl0 7 17713d-17
10 pallv16v8-10 and pallv16v8z-20 families logic diagram (continued) 034781112151619202324272831 32 39 40 47 48 55 0 3 4 7 8 1112 1516 1920 2324 2728 31 i 8 i 7 i 6 i 5 56 63 6 7 8 9 clk oe 1 1 0 x 1 0 sg1 sl0 3 1 1 0 x 1 0 sg1 sl0 1 1 1 0 x 1 0 sg1 sl0 0 1 1 0 x 1 0 sg1 sl0 2 oe/i 1 1 0 x 1 0 dq q 1 0 1 1 0 x 1 1 1 0 0 0 0 1 sg0 v cc sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 1 0 x 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc 0 x sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 2 0 x sg1 sl0 3 i/o 3 15 i/o 2 14 i/o 1 13 i/o 0 12 11 sl1 3 sl1 2 sl1 1 sl1 0 9 sl0 0 gnd 10 17713d-18
pallv16v8-10 (com?) 11 absolute maximum ratings storage temperature . . . . . . . . . . . . . .-65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . .-55 c to +125 c supply voltage with respect to ground . . . . . . . . . . . . . . . -0.5 v to +7.0 v dc input voltage . . . . . . . . . . . . . . . . . -0.5 v to 5.5 v dc output or i/o pin voltage . . . . . . . . . . . . . . . . . . . . . . -0.5 v to 5.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latch-up current (t a = 0 c to 75 c) . . . . . . . . . . . . . . . . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0 c to +75 c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +3.0 v to +3.6 v operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i il and i ozl ). 3. not more than one output should be shortened at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is guaranteed worst case under test conditions. refer to the i cc vs. frequency graph for typical measurements. parameter symbol parameter description test conditions min max unit v oh output high voltage v in = v ih or v il v cc = min i oh = ? ma 2.4 v i oh = ?5 ma v cc - 0.2 v v v ol output low voltage v in = v ih or v il v cc = min i ol = 2 ma 0.4 v i ol = 100 ma 0.2 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 5.5 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = v cc , v cc = max (note 2) 10 ? i il input low leakage current v in = 0 v, v cc = max (note 2) ?00 ? i ozh off-state output leakage current high v out = v cc , v cc = max, v in = v ih or v il (note 2) 10 ? i ozl off-state output leakage current low v out = v cc , v cc = max, v in = v ih or v il (note 2) -100 ? i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) -50 -130 ma i cc supply current outputs open (i out = 0 ma), v cc = max, f = 15 mhz (note 4) 55 ma
12 pallv16v8-10 (com?) capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d whe re capacitance may be affected. switching characteristics over commercial operating ranges 1 notes: 1. see ?witching test circuit?for test conditions. 2. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d whe re frequency may be affected. 3. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) - ts. parameter symbol parameter description test condition typ unit c in input capacitance v in = 2.0 v v cc - 3.3 v, t a = 25?, f = 1 mhz 5pf c out output capacitance v out = 2.0 v 8 pf parameter symbol parameter description -10 unit min max t pd input or feedback to combinatorial output (note 2) 10 ns t s setup time from input or feedback to clock 7 ns t h hold time 0 ns t co clock to output 7ns t wl clock width low 6 ns t wh high 6 ns f max maximum frequency (notes 2 and 3) external feedback 1/(t s + t co ) 71.4 mhz internal feedback (fcnt 1/(t s + t cf ) 83.3 mhz no feedback 1/(t s + t h ) 83.3 mhz t pzx oe to output enable 10 ns t pxz oe to output disable 10 ns t ea input to output enable using product term control 12 ns t er input to output disable using product term control 12 ns
pallv16v8z-20 (ind) 13 absolute maximum ratings storage temperature . . . . . . . . . . . . . .-65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . .-55 c to +125 c supply voltage with respect to ground . . . . . . . . . . . . . . . -0.5 v to +7.0 v dc input voltage . . . . . . . . . . . . . . . . . -0.5 v to 5.5 v dc output or i/o pin voltage . . . . . . . . . . . . . . . . . . . . . . -0.5 v to 5.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latch-up current (t a = -40 c to 85 c) . . . . . . . . . . . . . . . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . -40 c to +85 c supply voltage (v cc ) with respect to ground. . . . . . . . . . . . . . . +3.0 v to +3.6 v operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over industrial operating ranges note: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is guaranteed worst case under test conditions. refer to the i cc vs. frequency graph for typical measurements. parameter symbol parameter description test conditions min max unit v oh output high voltage v in = v ih or v il v cc = min i oh = ? ma 2.4 v i oh = ?5 ? v cc ?0.2 v v v ol output low voltage v in = v ih or v il v cc = min i ol = 2 ma 0.4 v i ol = 100 ? 0.2 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 5.5 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = v cc , v cc = max (note 2) 10 ? i il input low leakage current v in = 0 v, v cc = max (note 2) ?0 ? i ozh off-state output leakage current high v out = v cc , v cc = max, v in = v ih or v il (note 2) 10 ? i ozl off-state output leakage current low v out = v cc , v cc = max, v in = v ih or v il (note 2) -10 ? i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) -15 -75 ma i cc supply current outputs open (i out = 0 ma) v cc = max, f = 15 mhz (note 4) f = 0 mhz 30 ? f = 15 mhz 45 ma
14 pallv16v8z-20 (ind) capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d whe re capacitance may be affected. switching characteristics over industrial operating ranges 1 notes: 1. see ?witching test circuit?for test conditions. 2. this parameter is tested in standby mode. when the device is not in standby mode, the t pd will typically be about 2 ns faster. 3. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d whe re frequency may be affected. 4. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) - t s . parameter symbol parameter description test condition typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25?, f = 1 mhz 5pf c out output capacitance v out = 2.0 v 8 pf parameter symbol parameter description -20 unit min max t pd input or feedback to combinatorial output (note 2) 20 ns t s setup time from input or feedback to clock 15 ns t h hold time 0 ns t co clock to output 10 ns t wl clock width low 8 ns t wh high 8 ns f max maximum frequency (notes 3 and 4) external feedback 1/(t s + t co ) 40 mhz internal feedback (fcnt) 1/(t s + t cf ) 50 mhz no feedback 1/(t s + t h ) 66.7 mhz t pzx oe to output enable 20 ns t pxz oe to output disable 20 ns t ea input to output enable using product term control 20 ns t er input to output disable using product term control 20 ns
pallv16v8-10 and pallv16v8z-20 families 15 switching waveforms notes: 1. v t = 1.5 v for input signals and v cc /2 for output signals. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns to 5 ns typical. t pd input or feedback combinatorial output v t v to 17713d-7 a. combinatorial output v t v to input output d. input to output disable/enable 17713d-10 t er t ea v t input or feedback registered output b. registered output 17713d-8 t s t co v to t h v t clock t wh clock c. clock width v t t wl 17713d-9 v t v to oe output e. oe to output disable/enable 17713d-11 t pzx t pxz v oh - 0.5v v ol + 0.5v v oh - 0.5v v ol + 0.5v
16 pallv16v8-10 and pallv16v8z-20 families key to switching waveform switching test circuit speci?ation s 1 s 2 c l r 1 r 2 measured output value t pd , t co closed closed 30 pf 1.6k 1.6k v cc /2 t pzx , t ea z h: open z l: closed z h: closed z l: open v cc /2 t pxz , t er h z: open l z: closed h z: closed l z: open 5 pf h z: v oh ?0.5 v l z: v ol + 0.5 v ks000010-pal must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs 17713d-12 c l output r 1 r 2 s 1 test point v cc s 2
pallv16v8-10 and pallv16v8z-20 families 17 typical i cc characteristics v cc = 3.3 v, t a = 25 c 150 125 100 75 50 25 0 01020304050 frequency (mhz) i cc (ma) 17713d-13 the selected ?ypical pattern utilized 50% of the device resources. half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. half of the available product terms were used for each macrocell. on any vector, half of the outputs were switching. by utilizing 50% of the device, a midpoint is de?ed for i cc . from this midpoint, a designer may scale the i cc graphs up or down to estimate the i cc requirements for a particular design. i cc vs. frequency pallv16v8-10 pallv16v8z-20
18 pallv16v8-10 and pallv16v8z-20 families endurance characteristics the pallv16v8 is manufactured using vantis?advanced electrically-erasable (ee) cmos process. this technology uses an ee cell to replace the fuse link used in bipolar parts. as a result, devices can be erased and reprogrammed? feature which allows 100% testing at the factory. robustness features the pallv16v8 has some unique features that make it extremely robust, especially when operating in high-speed design environments. pull-up resistors on inputs and i/o pins cause unconnected pins to default to a known state. input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. a special noise ?ter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns. input/output equivalent schematics symbol parameter test conditions value unit t dr min pattern data retention time max storage temperature 10 years max operating temperature 20 years n max reprogramming cycles normal programming conditions 100 cycles 17713d-15 typical input typical output preload circuitry esd protection and clamping feedback input v cc v cc > 50 k ? v cc programming voltage detection positive overshoot filter programming circuitry provides esd protection and clamping programming pins only > 50 k ? v cc 5-v protection 17713d-14
pallv16v8-10 and pallv16v8z-20 families 19 power-up reset the pallv16v8 has been designed with the capability to reset during system power-up. following power-up, all ?p-?ps will be reset to low. the output state will be high independent of the logic polarity. this feature provides extra ?xibility to the designer and is especially valuable in simplifying state machine initialization. a timing diagram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to ensure a valid power-up reset. these conditions are: the v cc rise must be monotonic. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions min max unit t pr power-up reset time 1000 ns see switching characteristics t s input or feedback setup time t wl clock width low 17713d-16 t pr t wl t s 2.7 v v cc power registered output clock figure 3. power-up reset waveform
20 pallv16v8-10 and pallv16v8z-20 families typical thermal characteristics measured at 25 c ambient. these parameters are not tested. plastic jc considerations the data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. the heat- ?w paths in plastic-encapsulated devices are complex, making the jc measurement relative to a speci? location ion the package surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the pack age. furthermore, jc tests on packages are performed in a constant temperature. therefore, the measurements can only be used in a similar environment. parameter symbol parameter description typ unit pdip plcc jc thermal impedance, junction to case 20 19 ?/w ja thermal impedance, junction to ambient 65 57 ?/w jma thermal impedance, junction to ambient with air ?w 200 lfpm air 58 41 ?/w 400 lfpm air 51 37 ?/w 600 lfpm air 47 35 ?/w 800 lfpm air 44 33 ?/w
pallv16v8-10 and pallv16v8z-20 families 21 connection diagrams (top view) 1 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 12 13 i 3 i 4 i 5 i 6 i 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 oe/i 9 i/o 0 i/o 1 gnd i 8 clk/i 0 v cc i/o 7 i 1 i 2 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 14 13 12 11 v cc clk/i i i i i i i i i gnd i/o i/o i/o i/o i/o i/o i/o i/o oe/i 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 9 17713d-2 plcc dip/soic note: pin 1 is marked for orientation. 17713d-3 pin designations clk = clock gnd = ground i = input i / o = input/output nc = no connect v cc = supply voltage
22 pallv16v8-10 and pallv16v8z-20 families ordering information commercial and industrial products vantis programmable logic products for industrial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: speed ?0 = 10 ns t pd ?0 = 20 ns t pd valid combinations list con?urations planned to be supported in volume for this device. consult the local vantis sales of?e to con?m availability of speci? valid combinations and to check on newly released number of array inputs operating conditions c = commercial (0 c to +75 c) i = industrial (?0 c to 85 c) number of outputs output type v = versatile technology lv = low-voltage family type pal = programmable array logic package type p = 20-pin plastic dip (pd 020) j = 20-pin plastic leaded chip carrier (pl 020) s = 20-pin plastic gull-wing small outline package (so 020) valid combinations pallv16v8-10 pc, jc, sc pallv16v8z-20 pi, ji valid combinations pa l lv 1 6 v 8 z p c z = zero power (30 ? i cc standby) -10

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